Recently, there has been actively developed thin film transistors (TFT's) for the purpose of the application of them to image display devices for plane type displays. While polycrystalline semiconductor TFTs have advantages of high performance, high reliability and so on in comparison with those which use an amorphous semiconductor thin film, they are disadvantageous in that a high temperature is required to form a thin film. Accordingly, studies on and the application of a technique of crystallization of amorphous TFTs obtained by irradiating laser beams, which unnecessitates high temperature processing for the production of polycrystalline semiconductor thin films, have been actively conducted.
An attempt of reducing unwanted capacitance between the gate and the drain of a TFT in order to improve the operating speed has been made. In this case, a method of forming a gate electrode (hereinbelow, referred to as a gate) in a self-aligning manner with respect to a source electrode (hereinbelow, referred to as a source) and a drain electrode (hereinbelow, referred to as a drain) is remarkably effective.
A conventional process of forming a polycrystalline TFT with use of laser beams wherein a source-drain region is formed in a self-aligning manner with respect to the gate by an ion implantation method will be described with reference to FIG. 3. FIG. 3a is a cross-sectional view showing the initial stage of the conventional process for preparing the TFT, and FIG. 3b is a cross-sectional view showing the stage next to the stage as shown in FIG. 3a.
First of all, a passivation film 42 and an amorphous semiconductor layer 43 are deposited on an insulating substrate 41. Then, laser beams are irradiated on the laminated article to form a polycrystalline portion in the amorphous semiconductor layer 43. A pattern of polycrystalline semiconductor thin film 46 is formed on the passivation layer 42 by a photolithography method. A gate insulating film 44 and an electric conductive material 45 which serves as the gate electrode are deposited on the polycrystalline semiconductor thin film 46. Again, a pattern of gate is formed on the electric conductive material 45 by the photolithography method. In this case, the gate insulating film is etched to have the same pattern as the gate. Impurity ions are doped in the polycrystalline semiconductor layer 46 by the ion implantation method while the gate is used as a mask, followed by heat treating to effect impurity ion activation, whereby the source-drain region is formed. Further, an interlayer insulating film is formed on the source-drain region, and contact holes are formed in it. Thus, the source and the drain are respectively formed on the contact holes.
Such a conventional method wherein the impurity ions are activated by the heat treatment has the following disadvantage. Namely, when a material having good processability and a low heat resistance, such as glass, is used as the substrate, the material can not be heated at a sufficiently high temperature for the activation of the impurity ions, hence, the resistance in the source-drain region can not sufficiently be reduced. Further, a demand of using a material having good heat resistance such as quartz (which, on the other hand, deteriorates processability) in order to obtain a heat treatment of a sufficiently high temperature, is contrary to a demand of using a substrate having a large surface area. Accordingly, the conventional technique is insufficient to realize a display having a large surface area and to prepare a plurality of thin film products from a single substrate having a large surface area in order to reduce the manufacturing cost.